The present invention claims the benefit of Korean Patent Application No. P2000-67429 filed in Korea on Nov. 14, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that obtains a sub-micron complementary metal-oxide semiconductor (CMOS) device or a high voltage CMOS device.
2. Discussion of the Related Art
Presently, 0.25-micron MOS transistors are an example of the continuing miniaturization of MOS transistors that have fallen in size from the micron range to the low sub-micron range in a few short years. The advantages of utilizing ever smaller MOS transistors are that these devices reduce the cost of providing logic functions due to the increased number of transistors that can be integrated into a single package, and extend the life of battery-operated devices due to the lower voltage requirements of the smaller transistors.
One problem with utilizing current-generation 0.25-micron transistors, however, is that these transistors often function poorly when required to provide analog and mixed-signal functions due to the higher leakage currents and smaller dynamic ranges of these transistors.
With digital transistors, higher leakage currents contribute to increased power dissipation whereas leakage currents in analog transistors are particularly problematic in that these currents may render some analog circuits completely non-functional or lead to random errors. The higher leakage current in deep sub-micron processes is attributed to non-complete turn-off of the transistors due to the low threshold voltages. This is particularly true for very short channel transistors.
With respect to the dynamic range, current-generation 0.25 micron devices typically operate off of a 2.5-volt supply voltage, whereas previous generation 0.35 and 0.5 micron devices commonly operated off of 3.3 and 5-volt supply voltages, respectively. Thus, current-generation MOS transistors provide approximately two-thirds to one-half of the dynamic range of the older devices.
One solution to this problem is to utilize the 0.25-micron transistors when implementing the digital functions of a circuit, and the 0.35 or 0.5-micron transistors when implementing the analog or mixed-signal functions of the circuit.
A related art semiconductor device will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view showing a structure of the related art semiconductor device.
As shown in FIG. 1, a related art semiconductor device includes a semiconductor substrate 11, a barrier film 12, a gate electrode 14, an insulating sidewall 15, a lightly doped n-type impurity region 16, and a heavily doped n-type impurity region 16. The semiconductor substrate 11 includes an active region and a field region. The barrier film 12 is formed in the field region of the semiconductor substrate 11. The gate electrode 14 is formed on the active region of the semiconductor substrate 11 by interposing a gate insulating film 13 with a constant width. Then, the insulating sidewall 15 is formed at both sides of the gate electrode 14. The lightly doped n-type impurity region 16 is formed in a surface of the semiconductor substrate 11 at both sides of the gate electrode 14. The heavily doped n-type impurity region 17 is formed in a surface of the semiconductor substrate 11 at both sides of the insulating sidewall 15 in a shallower depth than a depth of the lightly doped n-type impurity region 16.
However, the related art semiconductor device has the following problems.
The device characteristics are determined by a size of the insulating sidewall formed at both sides of the gate electrode, a depth of junction, and a density of junction. Therefore, there is a limitation to miniaturize the semiconductor device and to obtain high quality of the device.
Accordingly, the present invention is directed to a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device that obtains miniaturization of a CMOS device and high quality of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor device includes a semiconductor substrate, a barrier film in a field region of the semiconductor substrate, first and second conductivity-type well regions in the semiconductor substrate and divided by the barrier film in a surface of the semiconductor substrate, a gate insulating film on an entire surface of the semiconductor substrate, a gate electrode on a region of the gate insulating film, a lightly-doped first conductivity-type impurity region formed in the second conductivity-type well region at a first side of the gate electrode, a lightly-doped second conductivity-type impurity region formed in the first conductivity-type well region at a second side of the gate electrode, a conductive pattern contacting the lightly-doped first and second conductivity-type impurity regions and having a constant distance from the gate electrode, an insulating film formed on the semiconductor substrate exposing upper portions of the gate electrode and the conductive pattern, and heavily-doped first and second conductivity-type impurity regions formed on the lightly-doped first and second conductivity-type impurity regions below the conductive pattern.
In another aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a barrier film in a field region of a semiconductor substrate, forming a first conductivity-type well region and a second conductivity-type well region, forming a gate insulating film on an entire surface of the semiconductor substrate, forming a plurality of contact holes in the gate insulating film, forming a conductive pattern inside each contact hole, forming a gate electrode on the gate insulating film between the conductive patterns, forming a lightly-doped first conductivity-type impurity region in the first conductivity-type well region at a first side of the gate electrode, forming a lightly-doped second conductivity-type impurity region in the second conductivity-type well region at a second side of the gate electrode, forming an insulating film on the semiconductor substrate to expose an upper portion of the conductive pattern and the gate electrode, and forming heavily-doped first and second conductivity-type impurity regions on the lightly-doped first and second conductivity-type impurity regions below the conductive pattern.
In another aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first conductivity-type well region in the semiconductor substrate, a plurality of lightly-doped second conductivity-type impurity regions formed in opposing portions of the first conductivity-type well region, a plurality of heavily-doped second conductive-type impurity regions formed in the lightly-doped second conductivity-type impurity regions, a gate insulating film on the semiconductor substrate, the gate insulating film having a plurality of first contact holes exposing portions of the heavily-doped second conductivity-type impurity regions, a gate electrode on the gate insulating film, the gate electrode having upper and lower surfaces, an insulating layer on the gate insulating film having upper and lower surfaces, the upper and lower surfaces of the insulating layer are coplanar with upper and lower surfaces of the gate electrode, respectively, a plurality of second contact holes formed in the insulating layer, each of the second contact holes are concentric with each of the plurality of first contact holes, and a plurality of conductive patterns in the first and second pluralities of contact holes contacting the heavily-doped second conductivity-type impurity regions, the conductive patterns having an upper surface coplanar with the upper surfaces of the gate electrode and insulating layer.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.